CODE                          TITLES 

VL0001    Bit-Swapping LFSR and Scan-Chain Ordering : A Novel Technique for Peak and Average Power                           Reduction in Scan-Based BIST 2009

VL0002    Self-Test Techniques for Crypto-Devices 2010

VL0003    Design of Low-Power High-Speed Truncation-Error-Tolerant Adder and ItsApplication in Digital Signal                   Processing 2010

VL0004    Hardware Implementation of RFID Mutual Authentication Protocol 2010

VL0005    Parallel and Pipeline Architectures for High-Throughput Computation ofMultilevel 3-D DWT 2010

VL0006    A Low-Cost VLSI Implementation for Efficient Removal of Impulse Noise 2010

VL0007    A High Bit Rate Serial-Serial Multiplier With On-the-Fly Accumulation by Asynchronous Counters 2011

VL0008    A Fast Locking All-Digital Phase-Locked Loop via Feed-Forward Compensation Technique 2011

VL0009    CMOS Full-Adders for Energy-Efficient Arithmetic Applications 2011

VL0010    A Digital CMOS Parallel Counter Architecture Based on State Look-Ahead Logic 2011

VL0011    Design of Fixed-Width Multipliers With Linear Compensation Function 2011

VL0012    Design of Sequential Elements for Low Power Clocking System 2011

VL0013    Efficient Pattern Matching Algorithm for Memory Architecture 2011

VL0014    High-Accuracy Fixed-Width Modified Booth Multipliers for Lossy Applications 2011

VL0015    Power-Efficient Explicit-Pulsed Dual-Edge Triggered Sense-AmplifierFlip-Flops 2011

VL0016    Reducing the Computation Time in (Short Bit-Width) Two’s Complement Multipliers 2011

VL0017    SET D-Flip Flop Design for Portable Applications 2011

VL0018    Adiabatic Technique for Energy Efficient Logic Circuits Design2011

VL0019    Memory Efficient Modular VLSI Architecture for High throughput andLow-Latency Implementation of                        Multilevel Lifting 2-D DWT 2011

VL0020    An Efficient Implementation of Floating Point Multiplier2011

VL0021    Radix-8 Booth Encoded Modulo 2^n-1 Multipliers With Adaptive Delay for High Dynamic Range Residue                 Number System 2011

VL0022    Efficient Design of a Hybrid Adder Using Quantum-Dot Cellular Automata2011

VL0023    VLSI Characterization of the Cryptographic Hash Function BLAKE2011

VL0024    BIST-Based Fault Diagnosis for Read-Only Memories2011

VL0025    Word-Level Finite Field Multiplier Using Normal Basis2011

VL0026    Low-Power and Area-Efficient Carry Select Adder2012

VL0027    Low-Power Pulse-Triggered Flip-Flop Design With Conditional Pulse-Enhancement Scheme 2012

VL0028    An Efficient TCAM-Based Implementation of Multi-pattern Matching UsingCovered State Encoding 2012

VL0029    Efficient Majority Logic Fault Detection With Difference-Set Codes for Memory Applications2012

VL0030    FFT Implementation with Fused Floating-Point Operations 2012

VL0031    High-Speed Architectures for Multiplication Using Reordered Normal Basis2012

VL0032    Low-Error and Hardware-Efficient Fixed-Width Multiplier by Using the Dual-Group Minor Input                                 Correction Vector to Lower Input Correction Vector Compensation Error2012

VL0033    On Modulo2^n+1 Adder Design2012

VL0034    Accumulator Based 3-Weight Pattern Generation2012

VL0035    Design of High Speed Vedic Multiplier using Vedic Mathematics Techniques2012 VL0036Separable                       Reversible Data-Hiding of Image2012

VL0037    A High-Accuracy Adaptive Conditional-Probability Estimator for Fixed-Width Booth Multipliers2012

VL0038    Investigating the Impact of Logic and Circuit Implementation on Full Adder Performance2012

VL0039    A Low-Power Single-Phase Clock Multiband Flexible Divider2012

VL0040    Area-Time Efficient Scaling-Free CORDIC Using Generalized Micro-Rotation Selection2012

VL0041    Design of an Error Detection and Data Recovery Architecture for Motion Estimation Testing                                   Applications2012

VL0042    Low Voltage and Low Power Divide-By-2/3 Counter Design Using Pass Transistor Logic Circuit                              Technique2012

VL0043    Measurement and Evaluation of Power Analysis Attacks on Asynchronous S-Box2012

VL0044    Effective and Efficient Approach for Power Reduction by Using Multi-Bit Flip-Flops 2013

VL0045    An Efficient De noising Architecture for Removal of Impulse Noise in Images 2013